With the dramatic increase in the size and block count of systems on a chip (SOC) over their application specific integrated circuit (ASIC) counterparts, engineers now need assistance beyond the clerical optimization tasks of placement and routing, they need assistance in applying their own expert abilities to design planning. This paper presents an investigation in applying expert systems to the automated .oorplanning of systems on a chip. The investigation presents some background on expert systems, and then the implementation and results of an expert system based edge placer for perimeter placement of floorplan hard blocks.