Philips has adopted a modular manufacturing test strategy for its SOCs that are part of the Nexperia™ Home Platform. The on-chip infrastructure that enables modular testing consists of wrappers and Test Access Mechanisms (TAMs). Optimizing that infrastructure minimizes the test application time and helps to fit the test data into the ATE vector memory. This paper presents the test architecture design for the chiplet-based PNX8550, the most complex Nexperia™ SOC designed to date. Significant savings in test time and TAM wires could be obtained with the help of TR-ARCHITECT, an in-house tool for automated design of SOC test architectures.