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Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04)
The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
ASCII Text
x 
 
Luigi Dadda, Marco Macchetti, Jeff Owen, "The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)," Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp. 30070, Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/DATE.2004.1269207,
author = {Luigi Dadda and Marco Macchetti and Jeff Owen},
title = {The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {3},
year = {2004},
issn = {1530-1591},
pages = {30070},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269207},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
SN - 1530-1591
SP
EP
A1 - Luigi Dadda,
A1 - Marco Macchetti,
A1 - Jeff Owen,
PY - 2004
KW - null
VL - 3
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Luigi Dadda, ALaRI-USI and Politecnico di Milano
Marco Macchetti, Politecnico di Milano
Jeff Owen, ST Microelectronics NV
After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.
Citation:
Luigi Dadda, Marco Macchetti, Jeff Owen, "The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)," date, vol. 3, pp.30070, Design, Automation and Test in Europe Conference and Exhibition Designers? Forum (DATE'04), 2004
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