Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
Citation:
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost, "CMOS Structures Suitable for Secured Hardware," date, vol. 2, pp.21414, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004