A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology

D
DATE
2004
Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Abstract - A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology

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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)

A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology (PDF)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	S. Bernardini, J.M. Portal, P. Masson, "A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 21404, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1269108, author = {S. Bernardini and J.M. Portal and P. Masson}, title = {A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2004}, issn = {1530-1591}, pages = {21404}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269108}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology SN - 1530-1591 SP EP A1 - S. Bernardini, A1 - J.M. Portal, A1 - P. Masson, PY - 2004 KW - null VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

S. Bernardini, L2MP-Polytech — IMT Technopôle de Ch?teau Gombert

J.M. Portal, L2MP-Polytech — IMT Technopôle de Ch?teau Gombert

P. Masson, L2MP-Polytech — IMT Technopôle de Ch?teau Gombert

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269108

Parametric failures in CMOS IC nanoelectronics, leads to strong detection problem. In order to develop new defect oriented test methods, it is of prime importance to study the behavior of the transistor affected by those kind of failures. In this paper, we present a new electrical transistor model, which allows to study the impact of gate oxide thickness drop. It is shown that electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

Citation:

S. Bernardini, J.M. Portal, P. Masson, "A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology," date, vol. 2, pp.21404, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004

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