Realizable Reduction for Electromagnetically Coupled RLMC Interconnects

D
DATE
2004
Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Abstract - Realizable Reduction for Electromagnetically Coupled RLMC Interconnects

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Rong Jiang Articles by Charlie Chung-Ping Chen

Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects (PDF)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Rong Jiang, Charlie Chung-Ping Chen, "Realizable Reduction for Electromagnetically Coupled RLMC Interconnects," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 21400, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1269106, author = {Rong Jiang and Charlie Chung-Ping Chen}, title = {Realizable Reduction for Electromagnetically Coupled RLMC Interconnects}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2004}, issn = {1530-1591}, pages = {21400}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269106}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Realizable Reduction for Electromagnetically Coupled RLMC Interconnects SN - 1530-1591 SP EP A1 - Rong Jiang, A1 - Charlie Chung-Ping Chen, PY - 2004 KW - null VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Rong Jiang, University of Wisconsin—Madison

Charlie Chung-Ping Chen, National Taiwan University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269106

This paper presents a realizable RLMC¹ reduction algorithm for extracted interconnect circuits based on two effective approaches: RL branch reduction and RC/LC node reduction. Our algorithm takes advantage of some structures existing extensively in interconnect circuits and hence has extremely fast execution time. It takes about 8 seconds to reduce a circuit of over 300,000 elements while maintaining 3% error and 75% element reduction ratio.

Citation:

Rong Jiang, Charlie Chung-Ping Chen, "Realizable Reduction for Electromagnetically Coupled RLMC Interconnects," date, vol. 2, pp.21400, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.