loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
Andre C. Nacul, University of California at Irvine
Tony Givargis, University of California at Irvine
In this work, we propose a combined Dynamic Voltage Scaling (DVS) and Dynamic Cache Reconfiguration (DCR) online algorithm that dynamically adapts the processor speed (i.e., voltage) and the cache subsystem to the workload requirements for the purposes of saving energy. The workload is considered to be a set of tasks with real-time deadlines. Our online algorithm is invoked as part of the OS scheduler, which performs standard earliest deadline first (EDF) task scheduling first. Then, our online algorithm, determines an ideal voltage/cache configuration for the current executing task.
Citation:
Andre C. Nacul, Tony Givargis, "Dynamic Voltage and Cache Reconfiguration for Low Power," date, vol. 2, pp.21376, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.