loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
ASCII Text
x 
 
Juan Luis Aragon, Dan Nicolaescu, Alex Veidenbaum, Ana-Maria Badulescu, "Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 21374, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/DATE.2004.1269095,
author = {Juan Luis Aragon and Dan Nicolaescu and Alex Veidenbaum and Ana-Maria Badulescu},
title = {Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {2},
year = {2004},
issn = {1530-1591},
pages = {21374},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269095},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
SN - 1530-1591
SP
EP
A1 - Juan Luis Aragon,
A1 - Dan Nicolaescu,
A1 - Alex Veidenbaum,
A1 - Ana-Maria Badulescu,
PY - 2004
KW - null
VL - 2
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Juan Luis Aragon, University of California at Irvine
Dan Nicolaescu, University of California at Irvine
Alex Veidenbaum, University of California at Irvine
Ana-Maria Badulescu, University of California at Irvine
This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.
Citation:
Juan Luis Aragon, Dan Nicolaescu, Alex Veidenbaum, Ana-Maria Badulescu, "Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors," date, vol. 2, pp.21374, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.