Accurate Estimation of Parasitic Capacitances in Analog Circuits

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Anuradha Agarwal Articles by Hemanth Sampath Articles by Veena Yelamanchili Articles by Ranga Vemuri

Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)

Accurate Estimation of Parasitic Capacitances in Analog Circuits (PDF)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri, "Accurate Estimation of Parasitic Capacitances in Analog Circuits," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 21364, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1269090, author = {Anuradha Agarwal and Hemanth Sampath and Veena Yelamanchili and Ranga Vemuri}, title = {Accurate Estimation of Parasitic Capacitances in Analog Circuits}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2004}, issn = {1530-1591}, pages = {21364}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269090}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Accurate Estimation of Parasitic Capacitances in Analog Circuits SN - 1530-1591 SP EP A1 - Anuradha Agarwal, A1 - Hemanth Sampath, A1 - Veena Yelamanchili, A1 - Ranga Vemuri, PY - 2004 KW - null VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Anuradha Agarwal, University of Cincinnati

Hemanth Sampath, University of Cincinnati

Veena Yelamanchili, University of Cincinnati

Ranga Vemuri, University of Cincinnati

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269090

This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis .ow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.

Citation:

Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri, "Accurate Estimation of Parasitic Capacitances in Analog Circuits," date, vol. 2, pp.21364, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.