A New Self-Checking Sum-Bit Duplicated Carry-Select Adder

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	Similar Articles Articles by E. S. Sogomonyan Articles by D. Marienfeld Articles by V. Ocheretnij Articles by M. G?ssel

Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder (PDF)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	E. S. Sogomonyan, D. Marienfeld, V. Ocheretnij, M. G?ssel, "A New Self-Checking Sum-Bit Duplicated Carry-Select Adder," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 21360, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1269087, author = {E. S. Sogomonyan and D. Marienfeld and V. Ocheretnij and M. G?ssel}, title = {A New Self-Checking Sum-Bit Duplicated Carry-Select Adder}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2004}, issn = {1530-1591}, pages = {21360}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269087}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A New Self-Checking Sum-Bit Duplicated Carry-Select Adder SN - 1530-1591 SP EP A1 - E. S. Sogomonyan, A1 - D. Marienfeld, A1 - V. Ocheretnij, A1 - M. G?ssel, PY - 2004 KW - null VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

E. S. Sogomonyan, University of Potsdam

D. Marienfeld, University of Potsdam

V. Ocheretnij, University of Potsdam

M. G?ssel, University of Potsdam

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269087

In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. For 64 bits area and maximal delay are determined by the SYNOPSYS CAD tool of the EUROCHIP project. Compared to a 64 bit carry-select adder without error detection the delay of the most significant sum-bit does not increase. The area is 170% of a 64 bit carry-select adder (without error detection and not code-disjoint).

Citation:

E. S. Sogomonyan, D. Marienfeld, V. Ocheretnij, M. G?ssel, "A New Self-Checking Sum-Bit Duplicated Carry-Select Adder," date, vol. 2, pp.21360, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004

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