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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
Taeweon Suh, Georgia Institute of Technology
Douglas M. Blough, Georgia Institute of Technology
Hsien-Hsin S. Lee, Georgia Institute of Technology
In embedded system-on-a-chip (SoC) applications, the demand for integrating heterogeneous processors onto a single chip is increasing. An important issue in integrating multiple heterogeneous processors on the same chip is to maintain the coherence of their data caches. In this paper, we propose a hardware/software methodology to make caches coherent in heterogeneous multiprocessor platforms with shared memory. Our approach works with any combination of processors that support invalidation-based protocols. As shown in our experiments, up to 58% performance improvement can be achieved with low miss penalty at the expense of adding simple hardware, compared to a pure software solution. Speedup can be improved even further as the miss penalty increases. In addition, our approach provides embedded system programmers a transparent view of shared data, removing the burden of software synchronization.
Citation:
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee, "Supporting Cache Coherence in Heterogeneous Multiprocessor Systems," date, vol. 2, pp.21150, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004
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