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Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
Architecture-Level Performance Estimation for IP-Based Embedded Systems
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
Kyoko Ueda, Osaka University
Keishi Sakanushi, Osaka University
Yoshinori Takeuchi, Osaka University
Masaharu Imai, Osaka University
In this paper, we propose a architecture-level performance estimation method for IP-based embedded systems using system-level profiling. Our method enables the performance estimation by the following procedures; 1) System-level profiling. 2) Automatic construction of the execution dependency graph (EDG) from the profile information. 3) Estimation of the system performance based on the EDG analysis. Our method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profile information. Experimental results show that our estimation method is about 10,000 times faster than the architecture-level simulations.
Citation:
Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai, "Architecture-Level Performance Estimation for IP-Based Embedded Systems," date, vol. 2, pp.21002, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004
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