Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04)
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
We present a compact, fully physical, analytical model for the propagation delay and the output transition time of deep-submicron CMOS gates. The model accounts for crosstalk effects, short-circuit currents, the input-output coupling capacitance and carrier velocity saturation effects. It is based on the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE simulations and other previously published models for different submicron technologies show significant improvements in terms of accuracy.
Citation:
J. L. Rosselló, J. Segura, "A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk," date, vol. 2, pp.20954, Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE'04), 2004