Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design

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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)

Concurrent Sizing, Vdd and V_th Assignment for Low-Power Design (PDF)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Ashish Srivastava, Dennis Sylvester, David Blaauw, "Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10718, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1268946, author = {Ashish Srivastava and Dennis Sylvester and David Blaauw}, title = {Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10718}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268946}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Concurrent Sizing, Vdd and V<sub>th</sub> Assignment for Low-Power Design SN - 1530-1591 SP EP A1 - Ashish Srivastava, A1 - Dennis Sylvester, A1 - David Blaauw, PY - 2004 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Ashish Srivastava, University of Michigan

Dennis Sylvester, University of Michigan

David Blaauw, University of Michigan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268946

We present a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on total power savings.

Citation:

Ashish Srivastava, Dennis Sylvester, David Blaauw, "Concurrent Sizing, Vdd and V_th Assignment for Low-Power Design," date, vol. 1, pp.10718, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004

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