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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
James Chin, University of Texas at Dallas
Mehrdad Nourani, University of Texas at Dallas
We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.
Citation:
James Chin, Mehrdad Nourani, "SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance," date, vol. 1, pp.10710, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004
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