Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)
Extremely Low-Power Logic
Paris, France
February 16-February 20
ISBN: 0-7695-2085-5
For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large logic blocks, interconnect becomes a main issue, that could be solved by on-chip optical interconnect. Nano-devices will also be presented, as a possibility to compute with nearly zero power, and compared to future 10 nanometers transistors.
Citation:
Christian Piguet, Jacques Gautier, Christoph Heer, Ian O?Connor, U. Schlichtmann, "Extremely Low-Power Logic," date, vol. 1, pp.10656, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004