Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04) A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks Paris, France February 16-February 20 ISBN: 0-7695-2085-5
This paper describes a new automatic clock-gating extraction working at the RT-level. The key features of our approach are: (i) Seamless merging with existing industrial design flows and commercial tools; (ii) High scalability to deal with large circuits; (iii) Improved quality of results with respect to available commercial tools; (iv) Smaller and well-controled overhead in speed and area. Experimental results, on a set of industrial RTL designs, demonstrate the viability and practical impact of our approach.
Citation:
Pietro Babighian, Luca Benini, Enrico Macii, "A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks," date, vol. 1, pp.10500, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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