Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques

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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke, "Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10442, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1268886, author = {Lutz Näthke and Volodymyr Burkhay and Lars Hedrich and Erich Barke}, title = {Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10442}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268886}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques SN - 1530-1591 SP EP A1 - Lutz Näthke, A1 - Volodymyr Burkhay, A1 - Lars Hedrich, A1 - Erich Barke, PY - 2004 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Lutz Näthke, University of Hanover

Volodymyr Burkhay, University of Hanover

Lars Hedrich, University of Hanover

Erich Barke, University of Hanover

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268886

We present an extended method of automatic behavioral model generation for nonlinear analog circuits. The focus is on a decrease of simulation time. A procedural model formulation approach is introduced, together with a new simpli.cation method based on the recognition of physical transistor properties of the element models. The simplification process is performed with respect to simulation time, and a hierarchical modeling approach is proposed. The result of these extensions are models with an obvious speed-up in simulation time compared to the simulation of the original netlists.

Citation:

Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke, "Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques," date, vol. 1, pp.10442, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004

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