A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

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Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Kris Tiri, Ingrid Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10246, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1268856, author = {Kris Tiri and Ingrid Verbauwhede}, title = {A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10246}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268856}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation SN - 1530-1591 SP EP A1 - Kris Tiri, A1 - Ingrid Verbauwhede, PY - 2004 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Kris Tiri, University of California at Los Angeles

Ingrid Verbauwhede, University of California at Los Angeles

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268856

This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make ?new? compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.

Citation:

Kris Tiri, Ingrid Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," date, vol. 1, pp.10246, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004

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