Digital Background Gain Error Correction in Pipeline ADCs

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	Similar Articles Articles by Antonio J. Gin? Articles by Eduardo J. Peral?as Articles by Adoraci? Rueda

Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04)

Paris, France

February 16-February 20

ISBN: 0-7695-2085-5

	ASCII Text	x
	Antonio J. Gin?, Eduardo J. Peral?as, Adoraci? Rueda, "Digital Background Gain Error Correction in Pipeline ADCs," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10082, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1268831, author = {Antonio J. Gin? and Eduardo J. Peral?as and Adoraci? Rueda}, title = {Digital Background Gain Error Correction in Pipeline ADCs}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10082}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268831}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Digital Background Gain Error Correction in Pipeline ADCs SN - 1530-1591 SP EP A1 - Antonio J. Gin?, A1 - Eduardo J. Peral?as, A1 - Adoraci? Rueda, PY - 2004 KW - Analog-to-Digital Converter KW - Pipeline ADC KW - Background Calibration KW - On-line Calibration VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Antonio J. Gin?, Instituto de Microelect?nica de Sevilla, Centro Nacional de Microelectr?nica

Eduardo J. Peral?as, Instituto de Microelect?nica de Sevilla, Centro Nacional de Microelectr?nica

Adoraci? Rueda, Instituto de Microelect?nica de Sevilla, Centro Nacional de Microelectr?nica

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268831

This paper presents a new digital technique for background calibration of gain errors in Pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.

Index Terms:

Analog-to-Digital Converter, Pipeline ADC, Background Calibration, On-line Calibration

Citation:

Antonio J. Gin?, Eduardo J. Peral?as, Adoraci? Rueda, "Digital Background Gain Error Correction in Pipeline ADCs," date, vol. 1, pp.10082, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004

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