In this paper we will review how the IP Reuse SoC design methodology has evolved from its first introduction, heavily based on IP Reuse to a state-of- the-art design flow based on soft and hard IP block and floorplanning tools. This will be illustrated in one complex SoC present in the broadband communication market today, which is a Set Top Box IC containing a proprietary 64-bits processor and some general-purpose blocks, along with dedicated functions specifically designed by STMicroelectronics. In order to manage designs of this complexity, a top-down, block-based design style, relying on automatic floorplanning tools will be described. This design style is using the classical 'divide-and-conquer' strategy and is thus enabling a concurrent development process, guaranteeing timing convergence and correct chip assembly.