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Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum)
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
ASCII Text
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Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates, "Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 20088, Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum), 2003.
 
 
BibTex
x
 
@article{ 10.1109/DATE.2003.1186677,
author = {Franco Carbognani and Christopher K. Lennard and C. Norris Ip and Allan Cochrane and Paul Bates},
title = {Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {2},
year = {2003},
issn = {1530-1591},
pages = {20088},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.1186677},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard
SN - 1530-1591
SP
EP
A1 - Franco Carbognani,
A1 - Christopher K. Lennard,
A1 - C. Norris Ip,
A1 - Allan Cochrane,
A1 - Paul Bates,
PY - 2003
KW - null
VL - 2
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Franco Carbognani, Cadence European Labs
C. Norris Ip, Cadence Design Systems
Allan Cochrane, ARM Ltd
Paul Bates, ARM Ltd

The increasing complexity of Systems on Chip (SoC) has introduced the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench Specification and monitoring, facilitate this SoC modeling. However, an obstacle to the adoption of abstract modeling as standard design practice is the lack of well establishes methodologies for the assessment of model precision. We describe such a methodology based on the SystemC Verification Standard implemented by Cadence's TestBuilder-SC. This methodology enables comparison of high-level (transaction level) SoC models in SystemC against implementation RTL models.

An application of the methodology is presented, based on the AMBA Class Library (ACL) for SystemC being developed by ARM in collaboration with EDA partners. The key elements of the methodology are:

  • 1. A completely reusable testbench that can be used for simulation and verification of the design at both high-level (transaction level) of abstraction and RTL implementation level.
  • 2. A single database format is used so that data collected from simulations at each level can easily be processed and compared

    • We present an example of effective validation of ARM PrimeXsys-platform IP components against their RTL implementation.

    Citation:
    Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates, "Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard," date, vol. 2, pp.20088, Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum), 2003
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