SPIN: A Scalable, Packet Switched, On-Chip Micro-Network

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Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum)

Munich, Germany

March 03-March 07

ISBN: 0-7695-1870-2

	ASCII Text	x
	Adrijean Adriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino, "SPIN: A Scalable, Packet Switched, On-Chip Micro-Network," Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 20070, Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum), 2003.

	BibTex	x
	@article{ 10.1109/DATE.2003.10240, author = {Adrijean Adriahantenaina and Hervé Charlery and Alain Greiner and Laurent Mortiez and Cesar Albenes Zeferino}, title = {SPIN: A Scalable, Packet Switched, On-Chip Micro-Network}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {2}, year = {2003}, issn = {1530-1591}, pages = {20070}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10240}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - SPIN: A Scalable, Packet Switched, On-Chip Micro-Network SN - 1530-1591 SP EP A1 - Adrijean Adriahantenaina, A1 - Hervé Charlery, A1 - Alain Greiner, A1 - Laurent Mortiez, A1 - Cesar Albenes Zeferino, PY - 2003 KW - Systems-on-Chip KW - Networks-on-Chip KW - Embedded Systems VL - 2 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Adrijean Adriahantenaina, UPMC/LIP6

Hervé Charlery, UPMC/LIP6

Alain Greiner, UPMC/LIP6

Laurent Mortiez, UPMC/LIP6

Cesar Albenes Zeferino, UFRGS

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10240

This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.

Index Terms:

Systems-on-Chip, Networks-on-Chip, Embedded Systems

Citation:

Adrijean Adriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino, "SPIN: A Scalable, Packet Switched, On-Chip Micro-Network," date, vol. 2, pp.20070, Design, Automation and Test in Europe Conference and Exhibition (DATE'03 Designers' Forum), 2003

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