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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
ASCII Text
x 
 
Ivo Schanstra, Ad.J. van de Goor, "Consequences of RAM Bitline Twisting for Test Coverage," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 11176, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.
 
 
BibTex
x
 
@article{ 10.1109/DATE.2003.10052,
author = {Ivo Schanstra and Ad.J. van de Goor},
title = {Consequences of RAM Bitline Twisting for Test Coverage},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2003},
issn = {1530-1591},
pages = {11176},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10052},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Consequences of RAM Bitline Twisting for Test Coverage
SN - 1530-1591
SP
EP
A1 - Ivo Schanstra,
A1 - Ad.J. van de Goor,
PY - 2003
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Ivo Schanstra, Infineon Technologies AG
Ad.J. van de Goor, Delft University of Technology
In order to reduce coupling effects between bit-lines in static or dynamic RAMs, bitline twisting can be used in the design. For testing, however, this has consequences for the to-be-used data backgrounds. A generic twisting scheme is introduced and the involved fault models are identified.
Citation:
Ivo Schanstra, Ad.J. van de Goor, "Consequences of RAM Bitline Twisting for Test Coverage," date, vol. 1, pp.11176, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
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