A new algorithm has been developed for the layout based direct electro-thermal simulation of integrated circuits. The advantage of the direct electro-thermal simulation over simulator coupling is, that very fast changes can also be considered, the drawback is that the thermal nodes are added to the number of nodes of the network to be simulated. The novelties of our method are the modeling and the solution of the thermal structure. This paper presents the algorithm of the time constant spectrum based FOSTER chain matrix thermal modeling, and the new algorithm of the coupled electro-thermal solution, where parts of the network, which represent the thermal behavior, are not computed in all steps of the iteration. This speeded up algorithm works both in the time-, and in the frequency domain. A simulation example demonstrates a typical application: the prediction of how the layout arrangement and the packaging of an analogue integrated circuit influence the electrical parameters.