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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Instruction Set Emulation for Rapid Prototyping of SoCs
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
ASCII Text
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Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel, "Instruction Set Emulation for Rapid Prototyping of SoCs," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10562, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.
 
 
BibTex
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@article{ 10.1109/DATE.2003.10090,
author = {Jürgen Schnerr and Gunter Haug and Wolfgang Rosenstiel},
title = {Instruction Set Emulation for Rapid Prototyping of SoCs},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2003},
issn = {1530-1591},
pages = {10562},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10090},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Instruction Set Emulation for Rapid Prototyping of SoCs
SN - 1530-1591
SP
EP
A1 - Jürgen Schnerr,
A1 - Gunter Haug,
A1 - Wolfgang Rosenstiel,
PY - 2003
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Jürgen Schnerr, FZI Forschungszentrum Informatik
Gunter Haug, FZI Forschungszentrum Informatik
Wolfgang Rosenstiel, FZI Forschungszentrum Informatik and Universit?t T?bingen
In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware behaviour of the emulated processor core is reproduced cycle accurately. This requires the use of hardware and software components. The hardware component consists of a board containing a VLIW processor and FPGAs. The software component is an instruction set simulator of the core running on the VLIW processor. The FPGAs are used for emulating the SoC bus of this processor core. This way the simulation of an instruction set of a processor core has been extended to a real emulation of this core that can be used for rapid prototyping.
Citation:
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel, "Instruction Set Emulation for Rapid Prototyping of SoCs," date, vol. 1, pp.10562, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
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