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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
On Modeling Cross-Talk Faults
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
Sujit T Zachariah, Intel Corporation
Yi-Shing Chang, Intel Corporation
Sandip Kundu, Intel Corporation
Chandra Tirumurti, Intel Corporation
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross coupling between interconnects is known to be a prime contributor to such failures. In this paper, we present novel techniques to model and prioritize capacitive cross-talk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on industrial circuits.
Citation:
Sujit T Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti, "On Modeling Cross-Talk Faults," date, vol. 1, pp.10490, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
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