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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
ASCII Text
x 
 
Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter, "Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10484, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.
 
 
BibTex
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@article{ 10.1109/DATE.2003.10016,
author = {Zaid Al-Ars and Ad J. van de Goor and Jens Braun and Detlev Richter},
title = {Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2003},
issn = {1530-1591},
pages = {10484},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10016},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
SN - 1530-1591
SP
EP
A1 - Zaid Al-Ars,
A1 - Ad J. van de Goor,
A1 - Jens Braun,
A1 - Detlev Richter,
PY - 2003
KW - stresses
KW - memory testing
KW - test optimization
KW - defect simulation
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Zaid Al-Ars, Delft University of Technology
Ad J. van de Goor, Delft University of Technology
Jens Braun, Infineon Technologies AG
Detlev Richter, Infineon Technologies AG
Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given test, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness.
Index Terms:
stresses, memory testing, test optimization, defect simulation
Citation:
Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter, "Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation," date, vol. 1, pp.10484, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
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