DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers

D
DATE
2003
Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Abstract - DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers

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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)

Munich, Germany

March 03-March 07

ISBN: 0-7695-1870-2

	ASCII Text	x
	Muhammad Nummer, Manoj Sachdev, "DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10212, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.

	BibTex	x
	@article{ 10.1109/DATE.2003.10047, author = {Muhammad Nummer and Manoj Sachdev}, title = {DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2003}, issn = {1530-1591}, pages = {10212}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10047}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers SN - 1530-1591 SP EP A1 - Muhammad Nummer, A1 - Manoj Sachdev, PY - 2003 KW - Delay-fault testing KW - high-performance testing KW - design for testability KW - design for delay testability VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Muhammad Nummer, University of Waterloo

Manoj Sachdev, University of Waterloo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10047

This paper presents a methodology for testing high-performance pipeline circuits with slow-spee testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. A clock timing circuit capable of achieving a timing resolution of 50ps in 0.18µm CMOS technology is presented. The design provides the ability to test the clock timing circuit itself.

Index Terms:

Delay-fault testing, high-performance testing, design for testability, design for delay testability

Citation:

Muhammad Nummer, Manoj Sachdev, "DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers," date, vol. 1, pp.10212, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003

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