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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)
Behavioural Modelling and Simulation of ΣΔ Modulators Using Hardware Description Languages
Munich, Germany
March 03-March 07
ISBN: 0-7695-1870-2
ASCII Text
x 
 
R. Castro-López, F. V. Fernández, F. Medeiro, A. Rodríguez-Vázquez, "Behavioural Modelling and Simulation of ΣΔ Modulators Using Hardware Description Languages," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10168, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.
 
 
BibTex
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@article{ 10.1109/DATE.2003.10004,
author = {R. Castro-López and F. V. Fernández and F. Medeiro and A. Rodríguez-Vázquez},
title = {Behavioural Modelling and Simulation of ΣΔ Modulators Using Hardware Description Languages},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2003},
issn = {1530-1591},
pages = {10168},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10004},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Behavioural Modelling and Simulation of ΣΔ Modulators Using Hardware Description Languages
SN - 1530-1591
SP
EP
A1 - R. Castro-López,
A1 - F. V. Fernández,
A1 - F. Medeiro,
A1 - A. Rodríguez-Vázquez,
PY - 2003
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
R. Castro-López, IMSE-CNM
F. V. Fernández, IMSE-CNM and Escuela Superior de Ingenieros
F. Medeiro, IMSE-CNM and Escuela Superior de Ingenieros
A. Rodríguez-Vázquez, IMSE-CNM and Escuela Superior de Ingenieros
Behavioural simulation is the common alternative to the costly electrical simulation of ΣΔ modulators (Sgr;Dgr;Ms). This paper explores the behavioural modelling and simulation of ΣΔMs by using hardware description languages (HDLs) and commercial behavioural simulators, as an alternative to the common special-purpose behavioural simulators. A library of building blocks, where a HDL has been used to model a complete set of circuit non-idealities influencing the performance of ΣΔMs, is introduced. Three alternatives for introducing ΣΔM topologies have been implemented. Experimental results of the simulation of a fourth-order 2-1-1 cascade multi-bit ΣΔM are given.
Citation:
R. Castro-López, F. V. Fernández, F. Medeiro, A. Rodríguez-Vázquez, "Behavioural Modelling and Simulation of ΣΔ Modulators Using Hardware Description Languages," date, vol. 1, pp.10168, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003
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