Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems

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Design, Automation and Test in Europe Conference and Exhibition (DATE'03)

Munich, Germany

March 03-March 07

ISBN: 0-7695-1870-2

	ASCII Text	x
	Dong Wu, Bashir M. Al-Hashimi, Petru Eles, "Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10090, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003.

	BibTex	x
	@article{ 10.1109/DATE.2003.10109, author = {Dong Wu and Bashir M. Al-Hashimi and Petru Eles}, title = {Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2003}, issn = {1530-1591}, pages = {10090}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10109}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems SN - 1530-1591 SP EP A1 - Dong Wu, A1 - Bashir M. Al-Hashimi, A1 - Petru Eles, PY - 2003 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Dong Wu, University of Southampton

Bashir M. Al-Hashimi, University of Southampton

Petru Eles, Link?pings University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10109

This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.

Citation:

Dong Wu, Bashir M. Al-Hashimi, Petru Eles, "Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems," date, vol. 1, pp.10090, Design, Automation and Test in Europe Conference and Exhibition (DATE'03), 2003

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