In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict top-down Hardware/Software Codesign paradigm using step-wise refinement techniques. Starting from a performance evaluation on the data-flow level using the OCAPI system, we partition the simulated high-level data-flow description into hardware and software modules. The hardware parts, described in Handel-C, are compiled and mapped to Xilinx Virtex 2000E FPGAs, and the software is executed on a PC processor that hosts the Virtex boards. Hardware/software interfacing and communication between processor and FPGA is established via the PCI bus by shared memory DMA transfers. This paper presents the methodology and illustrates the method with an example of a channel coder.