Advancing technology drives design technology and thus design automation (EDA). How to model interconnect, ho w to handle degradation of signal integrity and increasing power density are changing now, and have led to integrating logic and layout synthesis. Agressive gate sizing to control timing has become part of any modern back-end. F rom 0:13μ and down, chips will be more susceptive to breakdown during fabrication (antenna effect) or to wear out over time (electromigration) and dealing with these issues will require careful planning. More integration of fast and accurate analysis with a complete design ow (chip planning, synthesis, placement and routing) will be needed, and still, advancing complexity will affect design and verification. Using hundreds of millions of devices effectively will be possible only by reusing pre-designed intellectual property (IP) effectively and by addressing system-level issues in EDA. In the long term only more radical changes will keep us on Moore's track, changes that ultimately will have us depart from the two⁺-dimensional confinement and lead to multiple active layers, and changes that will affect deeply the face of EDA altogether.