We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and on-chip decompression. It makes effective use of frequency-directed run-length codes, internal scan chains, and boundary scan chains. The compression/ decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC. We show via analysis as well as through experiments that the proposed TRP scheme reduces testing time and allows the use of a slower tester with fewer I/O channels. Finally, we show that an uncompacted test set applied to an embedded core after on-chip decompression is likely to increase defect coverage.