Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of algorithms will no longer be able to cope with the kind of highly computing intensive applications of multimedia world. Nowadays approaches to deal with these limitations consist in the following: - The first, and most natural way to increase the computing power is obviously to decrease the cycle execution time, thanks to new silicon technology: The functional frequencies for the newcomers CPUs are now getting on the way to 2 GHz. - The second approach is co-design. The intended general purpose CPU will confide the computation of the most time demanding applications to a dedicated core. The most famous example are PC graphic cards which manage all the 2D and 3D display operations that even high-end CPUs are not able to handle efficiently. Both methods are not satisfying. The first one quickly finds its limitations in however limited functional frequencies and power consumption reduction, as the second requires the design of a new core for each intended algorithm. New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures.