Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

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2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02)

Paris, France

March 04-March 08

ISBN: 0-7695-1471-5

	ASCII Text	x
	M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, "Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification," Design, Automation and Test in Europe Conference and Exhibition, pp. 0285, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002.

	BibTex	x
	@article{ 10.1109/DATE.2002.998286, author = {M. Ciesielski and P. Kalla and Z. Zeng and B. Rouzeyre}, title = {Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2002}, isbn = {0-7695-1471-5}, pages = {0285}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2002.998286}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification SN - 0-7695-1471-5 SP EP A1 - M. Ciesielski, A1 - P. Kalla, A1 - Z. Zeng, A1 - B. Rouzeyre, PY - 2002 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

M. Ciesielski

P. Kalla

Z. Zeng

B. Rouzeyre

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2002.998286

This paper presents a new, compact, canonical graph-based representation, called Taylor Expansion Diagrams (TEDs). It is based on a general non-binary decomposition principle using Taylor series expansion. It can be exploited to facilitate the verification of high-level (RTL) design descriptions. We present the theory behind TEDs, comment upon its canonicity property and demonstrate that the representation has linear space complexity. Its application to equivalence checking of high-level design descriptions is discussed.

Citation:

M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, "Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification," date, pp.0285, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002

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