loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02)
Low Power Error Resilient Encoding for On-Chip Data Buses
Paris, France
March 04-March 08
ISBN: 0-7695-1471-5
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, etc. Transient delay and logic faults are likely to reduce the reliability of data transfers across data-path bus lines. This paper investigates how to deal with these errors in an energy efficient way. We could opt for error correction, which exhibits larger decoding overhead, or for the retransmission of the incorrectly received data word. Provided the timing penalty associated with this latter technique can be tolerated, we show that retransmission strategies are more effective than correction ones from an energy viewpoint, both for the larger detection capability and for the minor decoding complexity. The analysis was performed by implementing several variants of a Hamming code in the VHDL model of a processor based on the Sparc V8 architecture, and exploiting the characteristics of AMBA bus slave response cycles to carry out retransmissions in a way fully compliant with this standard on-chip bus specification.
Citation:
D. Bertozzi, L. Benini, G. de Micheli, "Low Power Error Resilient Encoding for On-Chip Data Buses," date, pp.0102, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.