Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits

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Design, Automation and Test in Europe (DATE '00)

Paris, France

March 27-March 30

ISBN: 0-7695-0537-6

	ASCII Text	x
	Dirk W. Hoffmann, Thomas Kropf, "Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits," Design, Automation and Test in Europe Conference and Exhibition, pp. 758, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840891, author = {Dirk W. Hoffmann and Thomas Kropf}, title = {Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {758}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840891}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits SN - 1530-1591 SP EP A1 - Dirk W. Hoffmann, A1 - Thomas Kropf, PY - 2000 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Dirk W. Hoffmann, University of T?bingen

Thomas Kropf, University of T?bingen

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840891

Boolean equivalence checking has turned out to be a powerful method for verifying combinational circuits and is already an integrated part of the design cycle. If equivalence checking fails, Design Error Diagnosis and Correction (DEDC) are performed. DEDC tries to locate and correct design errors fully automatically and can therefore considerably speed up the whole design cycle.

Citation:

Dirk W. Hoffmann, Thomas Kropf, "Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits," date, pp.758, Design, Automation and Test in Europe (DATE '00), 2000

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