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Design, Automation and Test in Europe (DATE '00)
A Versatile Built-In Self-Test Scheme for Delay Fault Testing
Paris, France
March 27-March 30
ISBN: 0-7695-0537-6
ASCII Text
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Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, D. Nikolos, "A Versatile Built-In Self-Test Scheme for Delay Fault Testing," Design, Automation and Test in Europe Conference and Exhibition, pp. 756, Design, Automation and Test in Europe (DATE '00), 2000.
 
 
BibTex
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@article{ 10.1109/DATE.2000.840889,
author = {Y. Tsiatouhas and Th. Haniotakis and A. Arapoyanni and D. Nikolos},
title = {A Versatile Built-In Self-Test Scheme for Delay Fault Testing},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {2000},
issn = {1530-1591},
pages = {756},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840889},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - A Versatile Built-In Self-Test Scheme for Delay Fault Testing
SN - 1530-1591
SP
EP
A1 - Y. Tsiatouhas,
A1 - Th. Haniotakis,
A1 - A. Arapoyanni,
A1 - D. Nikolos,
PY - 2000
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Y. Tsiatouhas, ISD S.A.
Th. Haniotakis, University of Athens
A. Arapoyanni, University of Athens
D. Nikolos, University of Patras
A new Built-In Self Test (BIST) scheme that can be used for both off-line production and periodic testing of delay faults as well as for concurrent detection of faults causing signal delays in the field is presented. The scheme is based on the IDDT monitoring of the outputs of the circuit under test (CUT) or functional circuit. The proposed scheme has minimal impact on the performance and silicon area of the design since the same response verifier circuit is used for both off-line and concurrent detection of errors in the field.
Citation:
Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, D. Nikolos, "A Versatile Built-In Self-Test Scheme for Delay Fault Testing," date, pp.756, Design, Automation and Test in Europe (DATE '00), 2000
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