All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses

D
DATE
2000
Design, Automation and Test in Europe (DATE '00)
Abstract - All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses

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Design, Automation and Test in Europe (DATE '00)

Paris, France

March 27-March 30

ISBN: 0-7695-0537-6

	ASCII Text	x
	Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee, "All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses," Design, Automation and Test in Europe Conference and Exhibition, pp. 527, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840836, author = {Chauchin Su and Yue-Tsang Chen and Mu-Jeng Huang and Gen-Nan Chen and Chung-Len Lee}, title = {All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {527}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840836}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses SN - 1530-1591 SP EP A1 - Chauchin Su, A1 - Yue-Tsang Chen, A1 - Mu-Jeng Huang, A1 - Gen-Nan Chen, A1 - Chung-Len Lee, PY - 2000 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Chauchin Su, National Central University

Yue-Tsang Chen, National Central University

Mu-Jeng Huang, National Central University

Gen-Nan Chen, National Central University

Chung-Len Lee, National Chiao-Tung University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840836

This paper proposes an all-digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers, and wires. Monitoring the changes in delay with the presence of the crosstalk plots the crosstalk profile. The distinguished features include all digital design and low hardware overhead. The SPICE simulation results prove the feasibility of the methodology.

Citation:

Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee, "All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses," date, pp.527, Design, Automation and Test in Europe (DATE '00), 2000

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