A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects

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Design, Automation and Test in Europe (DATE '00)

Paris, France

March 27-March 30

ISBN: 0-7695-0537-6

	ASCII Text	x
	Sungju Park, Taehyung Kim, "A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects," Design, Automation and Test in Europe Conference and Exhibition, pp. 458, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840311, author = {Sungju Park and Taehyung Kim}, title = {A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {458}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840311}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects SN - 1530-1591 SP EP A1 - Sungju Park, A1 - Taehyung Kim, PY - 2000 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Sungju Park, Hanyang University

Taehyung Kim, Hanyang University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840311

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique, which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction. Furthermore 2log(N+2) interconnect test patterns are proposed for both static and delay testing.

Citation:

Sungju Park, Taehyung Kim, "A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects," date, pp.458, Design, Automation and Test in Europe (DATE '00), 2000

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