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Design, Automation and Test in Europe (DATE '00)
Static Timing Analysis Taking Crosstalk into Account
Paris, France
March 27-March 30
ISBN: 0-7695-0537-6
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates the longest path of synchronous circuits taking the impact of crosstalk on gate delays into account. We show that passive modeling of the coupling capacitance can significantly underestimate the delay and that an assumption of permanent worst-case coupling unnecessarily overestimates it. Our method is validated by comparison to Spice simulations.
Citation:
M. Ringe, T. Lindenkreuz, E. Barke, "Static Timing Analysis Taking Crosstalk into Account," date, pp.451, Design, Automation and Test in Europe (DATE '00), 2000
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