Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJ?rg Henkel

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Design, Automation and Test in Europe (DATE '00)

Paris, France

March 27-March 30

ISBN: 0-7695-0537-6

	ASCII Text	x
	Tony D. Givargis, Frank Vahid, "Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJ?rg Henkel," Design, Automation and Test in Europe Conference and Exhibition, pp. 333, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840292, author = {Tony D. Givargis and Frank Vahid}, title = {Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJ?rg Henkel}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {333}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840292}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJ?rg Henkel SN - 1530-1591 SP EP A1 - Tony D. Givargis, A1 - Frank Vahid, PY - 2000 KW - System-on-a-chip KW - low power KW - estimation KW - intellectual property KW - cache KW - on-chip bus VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Tony D. Givargis, University of California at Riverside

Frank Vahid, University of California at Riverside

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840292

Index Terms:

System-on-a-chip, low power, estimation, intellectual property, cache, on-chip bus

Citation:

Tony D. Givargis, Frank Vahid, "Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJ?rg Henkel," date, pp.333, Design, Automation and Test in Europe (DATE '00), 2000

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