Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic

D
DATE
2000
Design, Automation and Test in Europe (DATE '00)
Abstract - Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic

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Design, Automation and Test in Europe (DATE '00)

Paris, France

March 27-March 30

ISBN: 0-7695-0537-6

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	Jovanka Ciric, Gin Yee, Carl Sechen, "Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic," Design, Automation and Test in Europe Conference and Exhibition, pp. 277, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840284, author = {Jovanka Ciric and Gin Yee and Carl Sechen}, title = {Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {277}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840284}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic SN - 1530-1591 SP EP A1 - Jovanka Ciric, A1 - Gin Yee, A1 - Carl Sechen, PY - 2000 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Jovanka Ciric

Gin Yee

Carl Sechen

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840284

This paper presents a new delay minimization and technology mapping algorithm for two-level structures (TLS) implemented using clock-delayed (CD) domino logic. We take advantage of CD domino's high-speed, large fan-in NOR and OR gates to increase the speed of a circuit by partial collapsing. The algorithm is delay-driven and the delays are obtained from a characterized CD domino library. The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CD domino with TLS, compared to static CMOS implementations generated by Synopsys. CD domino with TLS using our tools produced on average 44% faster circuits than CD domino benchmarks minimized and mapped using Synopsys. At last, the delay results for CD domino with TLS were on average 22% better than for standard domino.

Citation:

Jovanka Ciric, Gin Yee, Carl Sechen, "Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic," date, pp.277, Design, Automation and Test in Europe (DATE '00), 2000

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