Design, Automation and Test in Europe (DATE '00)
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing
Paris, France
March 27-March 30
ISBN: 0-7695-0537-6
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and inter-symbol interference (ISI) reduction in GSM/DCS systems. The temporal channel for the Viterbi receiver and the beam-former weights for the CCI rejection are estimated jointly by optimizing a suitable cost function for separable space-time channels. By taking into account nowadays integration capabilities provided by FPGA (Field Programmable Gate Array), it is demonstrated the feasibility of a single chip JSTE solution based on three processor architecture for carrier beam-forming, equalization and demodulation.
Citation:
U. Girola, A. Picciriello, D. Vincenzoni, "Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing," date, pp.181, Design, Automation and Test in Europe (DATE '00), 2000