Design, Automation and Test in Europe (DATE '00)
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
Paris, France
March 27-March 30
ISBN: 0-7695-0537-6
This paper describes CAS-BUS, a P1500 compatible Test Access Mechanism for Systems on a Chip. The TAM architecture is made up of a Core Access Switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.
Citation:
Mounir Benabdenebi, Walid Maroufi, Meryem Marzouki, "CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip," date, pp.141, Design, Automation and Test in Europe (DATE '00), 2000