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Design, Automation and Test in Europe (DATE '99)
Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs
Munich, Germany
March 09-March 12
ISBN: 0-7695-0078-1
Helena Krupnova, Institut National Polytechnique de Grenoble
Gabriele Saucier, Institut National Polytechnique de Grenoble
This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed in [12], but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques ([4],[14]). The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results ([12],[16]), and even outperforms them for biggest benchmarks.
Citation:
Helena Krupnova, Gabriele Saucier, "Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs," date, pp.587, Design, Automation and Test in Europe (DATE '99), 1999
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