In this paper, on-chip test circuitry performing the transient supply current measurement is presented. The introduced principle makes uses of the parasitic resistance of the supply connection to sense the dynamic supply current. Thus, the monitor does not cause any additional power supply voltage degradation and provides detection capabilities for open defects that usually cause a significant reduction of the I''7 current. The proposed monitor does not affect the performance of the CUT and can be efficiently used to test low-voltage CMOS circuits. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design has been implemented together with an experimental CMOS circuit using Alcatel-Mietec 0.7 mm CMOS technology and its processing is in progress. Evaluation results of the prototype test chips will be presented at the conference.