This paper presents a new integrated approach to logic optimization for sequential circuits. The approach is based on the Redundancy Addition and Removal algorithm, which is based on Automatic Test Pattern Generation (ATPG) techniques, and improves it using Symbolic Techniques based on BDDs. The advantage of the integrated approach lies in the ability of Symbolic Techniques to provide exact and extensive information about the sequential behavior of the portion of the circuit that is of interest to the logic optimization algorithm. Experimental results are provided that show the superiority of the approach to the original ATPG-based optimization approach.