Peter Feldman, Sharad Kapur, David E. Long, "Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics," Design, Automation and Test in Europe Conference and Exhibition, pp. 418, Design, Automation and Test in Europe (DATE '99), 1999.

@article{ 10.1109/DATE.1999.761158,
author = {Peter Feldman and Sharad Kapur and David E. Long},
title = {Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1999},
issn = {1530-1591},
pages = {418},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761158},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
SN - 1530-1591
SP
EP
A1 - Peter Feldman,
A1 - Sharad Kapur,
A1 - David E. Long,
PY - 1999
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -